FAQ

Sales & Support

Sales & Support

  • Q1How much power does this device consume?
  • APower consumption varies with operating conditions. For power consumption figures under typical operating conditions, refer to the document "Power Consumption" available at the following URL.

    https://global.epson.com/products_and_drivers/semicon/products/display_controllers/detail/s1d13513.html

  • Q2What is the maximum size of Main, PIP1 and PIP2 window?
  • AThe display performance is dependent on SDRAM data bus width and/or display panel clock frequency.
    Please consult a Seiko Epson sales representative for the maximum display size guidelines for these windows.
  • Q3Can you recommend specific manufacturers or models for SDRAM?
  • AEpson has no recommendation in particular. The SDRAM used on our S1D13513 evaluation board is available from Integrated Silicon Solution Inc. Please refer to Integrated Silicon Solution Inc. for SDRAM details.
  • Q4Do you offer an IBIS model?
  • AYes. Please refer to the documents contained in:

    S1D13513 IBIS model ZIP (96KB)

  • Q5Do you offer sample software for device initialization?
  • AYes. Sample software and device drivers are available at the URL below:

    https://global.epson.com/products_and_drivers/semicon/products/display_controllers/detail/s1d13513.html

  • Q6Do you offer an evaluation board?
  • AYes. Epson provides the S1D13513 evaluation board (S5U13513P00C100). Please contact a Seiko Epson sales representative for information on obtaining a board.
  • Q7Do you have any reference for PCB design of S1D13513?
  • AYes. Please refer to the evaluation board documents available at:

    https://global.epson.com/products_and_drivers/semicon/products/display_controllers/detail/s1d13513.html

  • Q8Are there any precautions when using synchronous host interface mode?
  • AYes, there are a couple of points to keep in mind.
    1. The maximum BUSCLK frequency is 50MHz.
    2. After a soft reset (Setting A55Ah to REG[0460h]), it takes 16 system clocks before asynchronous register access.
    3. Enable PCLK (set REG[0462h] bit-3 = 1b.)to access to synchronous register.
  • Q9Are there any precautions when using big-endian mode?
  • AYes. Byte swap is needed to access to the registers. Swap upper byte and lower byte in both read-out and write-in.
    On memory access, the S1D13513 automatically swap upper byte and lower byte.
  • Q10Is there a way to use the clock connecting directly to CLKI3 pin without divind(=1:1) LCDCLK (LCD panel clock)?
  • AYes. Use the register settings depicted below.
    These settings make direct use of CLKI3 as FPSHIFT. However, Setting 'REG[0446h] = 0000h (No clock dividing)' makes FPSHIFT polarity negative but this can be altered by changing 'REG[0800h]bit-7 FPSHIFT Polarity Select'.
    REG[0440h] 0002h (CLKI3 is the input clock)
    REG[0442h] 0000h (No clock dividing)
    REG[0444h] 0000h (CLKI3 is the clock for LCDDCLK. PLL2 is off.)
    REG[0446h] 0000h (No clock dividing)
  • Q11Are there any precautions when connecting an XGA panel?
  • ASet some values as follow within the panel specification.
    1. Set frequency of FPSHIFT nearest to minimum value.
    2. Set Horizontal Total (HT) nearest to maximum value.
    3. Set Vertical Total (VT) nearest to minimum value.
    4. Set frame rate nearest to minimum value.
  • Q12Do you have any examples of register settings for connecting panels?
  • AApplication notes are available through the URL below.

    http://global.epson.com/products_and_drivers/semicon/information/document_download/display_controllers.html

    Also please refer to the document "S1D13513 Panel Setting" of following URL.

    https://global.epson.com/products_and_drivers/semicon/products/display_controllers/detail/s1d13513.html

  • Q13Do you have any reference circuit for connecting crystal oscillator?
  • APlease consult the S1D13513 evaluation board document available at:

    https://global.epson.com/products_and_drivers/semicon/products/display_controllers/detail/s1d13513.html

  • Q14Please explain what to do for the pins in case that OSC1 and OSC2 are not used.
  • AIf you don't use OSC1 or OSC2, please use the following settings:
    OSCVDDx COREVDD
    OSCVSSx VSS
    OSCxI VSS
    OSCxO Open
    (x stands for 1 or 2.)
  • Q15Do you have any examples of register setting for SDRAM interface?
  • ARefer to the attached documents.

    S1D13513 SDRAM register settings PDF (11KB)

  • Q16Do you have any usage examples for sprite functionality?
  • AEpson has register setting examples for demonstration.
    We offer them to customer who bought the S1D13513 evaluation board. Please contact a Seiko Epson sales representative for more information.
  • Q17Are there any requirement of connection for JTAG related pins under normal operation mode?
  • ATRST pin for JTAG should be connected to RESET# pin or VSS.Please consult TRST description in "Table 5-7 Miscellaneous Pin Descriptions" on page 39 of the Hardware Specification for more details.

    https://global.epson.com/products_and_drivers/semicon/products/display_controllers/detail/s1d13513.html

  • Q18Who do I contact in the event the product fails to operate normally?
  • APlease contact your local Seiko Epson representative available at the following sales & Support.
    Sales & Support