Standard Cells

Standard cells are semi-custom ICs that enable optimally designed internal logic cells, memories such as ROM and RAM, CPU, and analog circuits to be implemented all on the same chip. As such, standard cells enable more design flexibility than do gate arrays, offer more advanced functionality and higher integration, and can be developed as system LSI optimized for the customer's needs. Such optimization leads to ever more compact, power-conserving devices.

Lineup

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Standard Cell Lineup

S1K80000 Series

Status MP
Series S1K80000 Series
Features
  • Based on 0.15µm CMOS process technology using 4/5-layer interconnect process
  • Internal gate delay: 43.9ps/1.8V, 2-input NAND Typ.
  • Lower power consumption (Internal cell: 0.039µW /MHz/gate 2-input NAND Typ.)
  • Drive performance (IOL=2,4,8,12mA at 3.3V)
Macro Cells RAM, ROM, Flash, LVDS, RSDS, various types of macro cells
Packages 48 to 256 pin QFP, PBGA, PFBGA, SQFN

S1K60000 Series

Status MP
Series S1K60000 Series
Features
  • Ultra large scale integration (0.25 µm CMOS, using 3-, 4- or 5-layer interconnect process,
    number of raw gates: 3,900,000 Max.)
  • High-speed operation (Internal gate delay: 106ps/2.5V, 2-input NAND Typ.)
  • Selectable power supply voltage: Using single power supply: (2.0 V, 2.5 V)
    Using dual power supply: (I/O: 3.0 V, Internal: 2.5 V, I/O: 3.3 V, Internal: 2.0 V)
  • Low power consumption (Internal cell: 0.09 µW/MHz/gate, 2.5V, Typ.)
  • Drivability (IOL = 0.1, 1, 3, 6, 12, 24 mA at 3.3 V, IOL = 0.1, 1, 3, 6, 9, 18 mA at 2.5 V,
    IOL = 0.05, 0.3, 1, 2, 3, 6 mA at 2.0 V)
Macro Cells RAM, ROM, Flash, MCU, PLL, LVDS, RSDS, and various types of macro cells can be implemented
Packages 48-pin to 256-pin QFP, PBGA, PFBGA, QFN