What is a Clock Generator?
A clock generator is a device that generates and supplies the synchronization signal (clock) that serves as the operating reference for digital circuits (such as CPUs, ICs, and circuit boards) and electronic systems.
In electronic devices, the timing of when operations occur is extremely important. A clock generator is used to determine and control that timing.
The primary role of a clock generator is to generate and distribute clock frequencies.
A fundamental waveform is generated using a crystal resonator or a crystal oscillator, and then the required frequencies for the system are produced by dividing or multiplying it through a PLL (Phase-Locked Loop) inside the clock generator.
Compared to typical PLL-based oscillators that provide only one or two outputs, clock generators offer multiple outputs ranging from as few as two to, in some cases, more than thirty. This allows them to be selected and used flexibly according to the number of destinations and the specific application requirements.
For applications where EMI noise reduction is required, clock generators equipped with a spread spectrum clocking (SSC) function are used to distribute accurate timing signals throughout the entire system.
Mechanism of a Clock Generator
As described above, the required "operating clocks" for the system are generated and supplied from an input clock by combining frequency division and multiplication using an internal PLL.
Input Clock:
The reference frequency (reference clock) is provided to the clock generator by a crystal resonator or a crystal oscillator.
Frequency Conversion:
Using the internal PLL and frequency divider circuits, frequency multiplication and division are performed to convert the reference frequency.
In PLL-based frequency conversion, there are broadly two types: Integer-N PLLs (integer division) and Fractional-N PLLs (fractional division).
An Integer-N PLL is a PLL architecture composed solely of an Integer-N divider (integer frequency divider).
Its advantages include a simple circuit structure and low noise and jitter. However, it has the disadvantage that it cannot generate frequencies that are not integer multiples or divisions. To overcome this limitation, the Fractional-N PLL is used.
A Fractional-N PLL is a PLL architecture that employs a Fractional-N divider in the feedback path.
Its advantage is that it enables fractional division, providing greater flexibility in frequency generation and allowing the creation of frequencies that cannot be achieved with integer division alone.
However, compared with Integer-N PLLs, it has the drawback of higher noise and jitter.
Output Clock:
After frequency conversion by the PLL, the operating clocks required by the system are output from each port.
(Integer-N Divider/Fractional-N Divider)
In many cases, each output stage is also equipped with a divider, allowing the frequency generated by the PLL to be further divided at each output and supplied as clock signals (Integer-N Divider / Fractional-N Divider).
Key Considerations for Selecting a Clock Generator
A clock generator should be selected based on factors such as the required system frequencies, jitter performance, number of output channels, and interface type.
Selection Based on Frequency
First, confirm the frequency requirements of the target digital circuits (such as CPUs, ICs, and circuit boards) and electronic systems. Based on the required frequencies (e.g., 25 MHz, 100 MHz, 156.25 MHz), select a clock generator that meets the specifications.
As mentioned above, if flexibility in frequency settings is required, it is necessary to use a clock generator that incorporates a Fractional-N PLL and Output Dividers.
Since the capabilities of a single device vary depending on the number of built-in PLLs and the type of dividers it includes, this can be considered the most important selection criterion.
Number of Channels (Outputs)
The required number of channels is determined by the number of target devices (such as FPGAs, CPUs, and PHYs).
If only a single output is needed, a simple clock supply using a crystal resonator or oscillator is generally preferred. However, if there are multiple destinations and requirements such as maintaining synchronization among them or reducing board space, a multi-output clock generator should be selected.
Output Levels (Output Formats)
The logic signal standard must match the input specifications of the destination devices
Since the supported formats depend on the receiving device, the system will not operate correctly if the clock is output in a different format. Therefore, it is essential to verify that the clock generator's output specifications are compatible with the input requirements of the target devices and to select one that provides the same format.
Examples of formats: HCSL (LP-HCSL), CMOS (LVCMOS), LVDS, PECL (LVPECL)
The output format should be selected based on the following criteria:
- Supported format of the destination device
- Clock frequency
Relatively low-speed clocks (up to around 50MHz):CMOS
High-speed clocks (several hundred MHz or higher): Differential clocks (such as HCSL or LVDS) - Noise and EMI requirements
Strict requirements: Differential clocks (such as HCSL or LVDS)
Standard requirements: CMOS
Jitter and Phase Noise
In high-speed serial communication applications (such as PCIe, 10G/100G Ethernet, and 5G), extremely low jitter (on the order of sub-picoseconds or several hundred femtoseconds) is required. Therefore, the clock generator must be selected based on the level of timing accuracy and signal integrity needed.
Spread Spectrum Clocking (SSC)
Spread Spectrum Clocking (SSC) is a noise reduction feature incorporated into clock generators.
Often simply referred to as an SS function, it works by slightly modulating the clock frequency to reduce the impact of EMI noise
. Instead of concentrating noise at a single frequency point, SSC spreads it across a wider frequency range, thereby reducing EMI peak emissions.
