Gate Arrays

Epson offers a full lineup of Gate Arrays, such as the 0.25 µm process S1L60000 Series, which feature high speed,high integration, and low power consumption.

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CMOS Gate Arrays : S1L70000 Series

Status MP
Series S1L70000 series
Features
  • Ultra large scale integration (0.18 μm CMOS, using 3-,4-,5-,6-layer interconnect process)
  • High-speed operation (43.6 ps internal gate delay at 1.8 V, with 2-input NAND Typ.)
  • Low power consumption (Internal cell: 0.077µW/MHz/gate at 1.8 V, with 2-input NAND Typ.)
  • Drivability (IOL = 2, 4, 8, 12 mA at 3.3 V, IOL = 1, 2, 4, 6 mA at 1.8 V, IOL = 0.75, 1.5, 3, 4.5 mA at 1.5 V )
  • RAM (synchronous type) and various types of macro cells can be implemented
Model Quadruple layer S1L70084 S1L70174 S1L70314
Quintruple layer S1L70085 S1L70175 S1L70315
Sextuple layer S1L70086 S1L70176 S1L70316
Total BC(Row gates) 86.6k 173.0k 316.5k
Usable gates Quadruple layer 64.9k 112.5k 205.7k
Quintruple layer 69.3k 121.1k 221.5k
Sextuple layer 73.6k 129.8k 237.4k
Total Lead Count
80μm 60 - -
70μm - 112 144
Delay Time Internal gates tpd = 43.6 ps (1.8 V, F/O 1, typical wire load)
Input buffer tpd = 181 ps (3.3 V, F/O 2, typical wire load)
Output buffer tpd = 1510 ps (3.3 V / 1.8V, CL = 15 pF)
I/O level LVCMOS, LVTTL, PCI-3.3V
Input mode LVCMOS, LVTTL, LVCMOS Schmitt, PCI-3V, Pull-up/Pull-down, Level shifter, Fail-safe, Gated
Output mode Normal, Open drain, 3-state, Bidirectional, Level shifter, Fail-safe, Gated

Note: Figures shown for usable gates are approximations. The actual number of usable gates varies according to the implemented circuitry.

CMOS Gate Arrays : S1L60000 Series

Status MP
Manual S1L60000 series design guide PDF (3,548KB)
Series S1L60000 series
Features
  • Ultra large scale integration (0.25 μm CMOS, using 3-, 4-layer interconnect process)
  • High-speed operation (107 ps internal gate delay at 2.5 V, with 2-input NAND Typ.)
  • Low power consumption (Internal cell: 0.18µW/MHz/gate at 2.5 V, with 2-input NAND Typ.)
  • Drivability (IOL = 0.1, 1, 3, 6, 12, 24 mA at 3.3 V, IOL = 0.1, 1, 3, 6, 9,18 mA at 2.5 V,IOL = 0.05, 0.3, 1, 2, 3, 6 mA at 2.0 V, IOL = 0.045, 0.27, 0.9, 1.8, 2.7, 5.4 mA at 1.8 V)
  • RAM (synchronous type, asynchronous type), PLL, and various types of macro cells can be implemented
Model Triple layer S1L60000 series spec table PDF
Quadruple layer
Total BC(Row gates)
Usable gates Triple layer
Quadruple layer
Total Lead Count
80μm
70μm
Delay Time Internal gates tpd = 107 ps (2.5 V, F/O 1, typical wire load)
Input buffer tpd = 270 ps (2.5 V, F/O 2, typical wire load)
Output buffer tpd = 1600 ps (2.5 V, CL = 15 pF)
I/O level CMOS, LVTTL, PCI-3.3V
Input mode CMOS, LVTTL, Pull-up/Pull-down, Schmitt, Level shifter, Fail-safe, Gated
Output mode Normal, Open drain, 3-state, Bidirectional, Level shifter, Fail-safe, Gated

Note: Figures shown for usable gates are approximations. The actual number of usable gates varies according to the implemented circuitry.

CMOS Gate Arrays : S1L50000 Series

Status MP
Manual S1L50000 series design guide PDF (3,481KB)
S1L50000 series 2.5 voltage library design guide PDF (1,846KB)
Series S1L50000 series
Features
  • Ultra large scale integration (0.35 μm CMOS, using 2-, 3- or 4-layer interconnect process)
  • High-speed operation (0.14 ns delay at 3.3 V, with 2-input power NAND Typ.)
  • Low power consumption (Internal cell: 0.7µW/MHz/gate at 3.3 V)
  • Drivability (IOL = 0.1, 1, 3, 8, 12, 24 mA, PCI at 5.0 V, IOL = 0.1, 1, 2, 6, 12 mA, PCI at 3.3 V,IOL = 0.1, 0.5, 1, 3, 6 mA at 2.5 V, IOL = 0.05, 0.3, 0.6, 2, 4 mA at 2.0 V)
  • RAM(asynchronous type), PLL, and various types of macro cells can be implemented
Model Double layer S1L50000 series spec table PDF
Triple layer
Quadruple layer
Total BC(Row gates)
Usable gates Double layer
Triple layer
Quadruple layer
Total Lead Count
80μm
70μm
Delay Time Internal gates tpd = 0.14 ns (3.3 V, F/O 2, typical wire load), 0.21 ns (2.0 V, F/O 2, typical wire load)
Input buffer tpd = 0.38 ns (5.0 V, F/O 2, typical wire load) Level shifter: 0.4 ns (3.3 V, F/O 2, typical wire load), 1.3 ns (2.0 V, F/O 2, typical wire load)
Output buffer tpd = 2.12 ns (5.0 V) Level shifter: 2.02 ns (3.3 V), 3.9 ns (2.0 V) CL = 15 pF
I/O level CMOS, LVTTL, PCI-5V, PCI-3.3V
Input mode LVTTL, CMOS, Pull-up/Pull-down, Schmitt, Fail-safe, Gated
Output mode Normal, Open drain, 3-state, Bidirectional, Fail-safe, Gated

Note: Figures shown for usable gates are approximations. The actual number of usable gates varies according to the implemented circuitry.

CMOS Gate Arrays : S1L5V000 Series

Status MP
Manual TBD
Series S1L5V000 series
Features
  • Large scale integration (0.35um CMOS, using 2-, 3-, 4-layer interconnect process)
  • High speed operation (internal gate delay: 0.19ns at 5V, 0.29ns at 3.3V, 2-input power NAND Typ.)
  • Low power consumption (Internal cell: 5V 1.3uW/MHz/BC, 3.3V 0.54uW/MHz/BC)
  • Drive capacity (IOL=0.1, 1, 3, 8, 12, 24mA at 5.0V, IOL=0.1, 1, 2, 6, 10mA at 3.3V)
Model Double layer
Metallization
S1L5V012 S1L5V042 - S1L5V112 - S1L5V252 - S1L5V482
*2
Triple layer S1L5V013 S1L5V043 S1X5V513
*1
S1L5V113 S1X5V523
*1
S1L5V253 S1X5V533
*1
S1L5V483
*2
Quadruple layer S1L5V014 S1L5V044 S1X5V514
*1
S1L5V114 S1X5V524
*1
S1L5V254 S1X5V534
*1
S1L5V484
*2
Total BC(Row gates) 8.9k 42.0k 26.0k 109.3k 90.3k 254.4k 235.0k 479.9k
Usable gates Double layer 2.7k 12.6k - 32.8k - 63.6k - 119.9k
Triple layer 5.4k 25.2k 14.3k 65.6k 49.7k 139.9k 129.3k 239.9k
Quadruple layer 6.2k 29.4k 16.9k 76.5k 58.7k 165.4k 152.8k 287.9k
Total Lead Count
48 104 168 256 308
Delay Time Internal gates tpd=0.19ns (5.0V operation, F/O=2, typical wiring load), tpd=0.29ns (3.3V operation, F/O=2, typical wiring load)
Input buffer tpd=0.45ns (5.0V operation, F/O=2, typical wiring load), tpd=0.55ns (3.3V operation, F/O=2, typical wiring load)
Output buffer tpd=2.07ns (5.0V operation, CL=15pF), tpd=2.95ns(3.3V operation, CL=15pF)
I/O level CMOS, TTL, LVTTL
Input mode TTL, LVTTL, CMOS, Pull-up/Pull-down, Schmitt, Fail-safe, Gated
Output mode Normal, Open-drain, 3-state, Bidirectional, Fail safe, Gated

Note: Figures shown for usable gates are approximations. The actual number of usable gates varies according to the implemented circuitry.

*1: Analog PLL built in master
*2: Under Development