About Epson Semiconductor
- Epson's Three Core Technologies
- Low Current Leakage Process - Process technology that dramatically reduces standby current
- Eco-friendly Power Algorithm - Algorithms for efficient utilization of the system power
- Low Power Analog IP - Analog IPs driven by the ultimately low possible power
- True Partnership
Epson's Three Core Technologies
With our three core technologies - low current leakage process technology that dramatically reduces standby current, system algorithms for highly efficient power utilization, and analog IPs optimally designed for low power consumption - Epson presents solutions for customers to develop applications that exceed there expectations.
We offer optimally-designed products, information and services in a most timely manner from the very beginning of your product development to volume production. We believe our support throughout all stages of your product cycle will lead to the adoption of Epson devices for your next products.
Low Current Leakage Process - Process technology that dramatically reduces standby current
We have been taking on the challenge of reducing standby current since we first developed the CMOS LSI for watches nearly 40 years ago. The technologies we have accumulated since then are utilized in a variety of advanced LSI devices - such as clock ICs whose standby current has been reduced to 1% that of previous devices. The reduction of standby current is a key issue for high-integration LSIs and SoC devices. For example, by isolating the timer and wake-up circuits from SoC, the standby current of equipment can be reduced to nano-ampere level. Epson meets customer's needs for substantial reduction of standby current with its unique low current leakage process know-how.
Eco-friendly Power Algorithm - Algorithms for efficient utilization of the system power
Epson's advanced LSIs are designed to minimize power consumption. we offer our solutions from both hardware and software to maximize the power efficiency for customer's entire system. For example, USB controllers reduce CPU load by optimizing data partitioning. Network controllers minimumize power consumption by processing network protocols. Watch ICs drive in the optimum clock frequency and operate by minimum power. To increase entire system power efficiency, Epson' offers optimized algorithm by our strong expertise in enhancing power utilization. Our services minimize customer's resources to develop the products and shorten the time to market.
Low Power Analog IP - Analog IPs driven by the ultimately low power
We have spent years developing unique technologies that reduce the power consumption of analog circuits. This work began with our CMOS LSIs for watches and has continued with the development of various low power management IPs such as DC/DC, LDO, Detector, and SWReg, as well as the development of low-power analog IPs such as ADC, PLL, and real-time clocks. By combining multiple analog IPs, we have achieved the low power operation indispensable to mobile equipment. Our low power analog IPs offer you strategic and competitive advantages, by realizing shorter time-to-market and low power products.
Offering timely our products, information, and services optimized to customers' products, we consistently support their whole business cycle from the parts selection for their new product, the development, the mass production to the next product planning. Based on our policy "think customer first", not to mention customized products, regarding standard products, we propose and offer our podcuts, services, support, and delivery with careful attention in detail to meet what customers would like. Epson seeks to build long, close, true partnerships with our customers, by offering them solutions that maximize their product value. We also hope to contribute with cutosmers to the environmental presevaton, safety and healthy, for the people and the society.