Display Controllers

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FAQ

Inquiry sheet

Please provide all appropriate details on the inquiry sheet provided and send the sheet to a Seiko Epson sales representative.

Inquiry sheet


Q1

How much power does this device consume?


A

Power consumption varies with operating conditions. Refer to the reference material , "S1D13513 power consumption" below, which shows power consumption figures under typical operating conditions.

http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=87&Itemid=435



Q2

What is the maximum size of Main, PIP1 and PIP2 window?


A

The display performance is dependent on SDRAM data bus width and/or display panel clock frequency.
Please consult a Seiko Epson sales representative for the maximum display size guidelines for these windows.



Q3

Can you recommend specific manufacturers or models for SDRAM?


A

Epson has no recommendation in particular. The SDRAM used on our S1D13513 evaluation board is available from Integrated Silicon Solution Inc. Please refer to Integrated Silicon Solution Inc. for SDRAM details.



Q4

Do you offer an IBIS model?


A

Yes. Please refer to the documents contained in:

S1D13513 IBIS model ZIP(96KB)



Q5

Do you offer sample software for device initialization or device drivers for Windows CE or Linux?


A

Yes. Sample software and device drivers are available at the URL below:

http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=87&Itemid=435



Q6

Do you offer an evaluation board?


A

Yes. Epson provides the S1D13513 evaluation board (S5U13513P00C100). Please contact a Seiko Epson sales representative for information on obtaining a board.



Q7

Do you have any reference for PCB design of S1D13513?


A

Yes. Please refer to the evaluation board documents available at:

http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=87&Itemid=435



Q8

Are there any precautions when using synchronous host interface mode?


A

Yes, there are a couple of points to keep in mind.

  1. The maximum BUSCLK frequency is 50MHz.
  2. After a soft reset (Setting A55Ah to REG[0460h]), it takes 16 system clocks before asynchronous register access.
  3. Enable PCLK (set REG[0462h] bit-3 = 1b.)to access to synchronous register.


Q9

Are there any precautions when using big-endian mode?


A

Yes. Byte swap is needed to access to the registers. Swap upper byte and lower byte in both read-out and write-in.
On memory access, the S1D13513 automatically swap upper byte and lower byte.



Q10

Is there a way to use the clock connecting directly to CLKI3 pin without divind(=1:1) LCDCLK (LCD panel clock)?


A

Yes. Use the register settings depicted below.
These settings make direct use of CLKI3 as FPSHIFT. However, Setting 'REG[0446h] = 0000h (No clock dividing)' makes FPSHIFT polarity negative but this can be altered by changing 'REG[0800h]bit-7 FPSHIFT Polarity Select'.

REG[0440h] 0002h (CLKI3 is the input clock)
REG[0442h] 0000h (No clock dividing)
REG[0444h] 0000h (CLKI3 is the clock for LCDDCLK. PLL2 is off.)
REG[0446h] 0000h (No clock dividing)


Q11

Are there any precautions when connecting an XGA panel?


A

Set some values as follow within the panel specification.

  1. Set frequency of FPSHIFT nearest to minimum value.
  2. Set Horizontal Total (HT) nearest to maximum value.
  3. Set Vertical Total (VT) nearest to minimum value.
  4. Set frame rate nearest to minimum value.


Q12

Do you have any examples of register settings for connecting panels?


A

Application notes are available through the URL below.

http://global.epson.com/products/semicon/products/download/lcd_controllers.html

Also please refer to the document “S1D13513 Panel Setting” of following URL.

http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=87&Itemid=435



Q13

Do you have any reference circuit for connecting crystal oscillator?


A

Please consult the S1D13513 evaluation board document available at:

http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=87&Itemid=435



Q14

Please explein what to do for the pins in case that OSC1 and OSC2 are not used.


A

If you don't use OSC1 or OSC2, please use the following settings:

OSCVDDx COREVDD
OSCVSSx VSS
OSCxI VSS
OSCxO Open

(x stands for 1 or 2.)



Q15

Do you have any examples of register setting for SDRAM interface?


A

Refer to the attached documents.

S1D13513 SDRAM register settings PDF(11KB)



Q16

Do you have any usage examples for sprite functionality?


A

Epson has register setting examples for demonstration.
We offer them to customer who bought the S1D13513 evaluation board. Please contact a Seiko Epson sales representative for more information.



Q17

Are there any requirement of connection for JTAG related pins under normal operation mode?


A

TRST pin for JTAG should be connected to RESET# pin or VSS.
Please consult TRST description in "Table 5-7 Miscellaneous Pin Descriptions" on page 39 for more details.

http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=87&Itemid=435



Q18

Please provide a contact address in the event of cases in which the product fails to operate normally.


A

Please contact a Seiko Epson sales representative.

Please provide all appropriate details on the inquiry sheet available through following URL and send the sheet to a Seiko Epson sales representative.

Inquiry sheet