ASICs

Text SizeSmallLarge

Standard cells are semi-custom ICs that enable optimally designed internal logic cells, memories such as ROM and RAM, CPU, and analog circuits to be implemented all on the same chip. As such, standard cells enable more design flexibility than do gate arrays, offer more advanced functionality and higher integration, and can be developed as system LSI optimized for the customer's needs. Such optimization leads to ever more compact, power-conserving devices.


Document download

Standard Cell Lineup

S1K70000Series

Status MP
Manual PDF S1K70000/S1X70000 Series 5V Tolerant Design Guide (5,390KB)
PDF S1K70000/S1X70000 Series Design Guide (5,891KB)
Series S1K70000Series
Features
  • Large scale integration (0.18 µm CMOS, using 3-,4-,5-, or 6-layer interconnect process, number of raw gates: 7,300,000 Max.)
  • High-speed operation (Internal gate delay: 38.9ps/1.8V, 2-input NAND Typ.)
  • Selectable supply voltage: Operation on single power supply (1.8V, 1.5V),
    Operation on dual power supply (I/O: 3.3V/internal: 1.8V, I/O: 2.5V/internal: 1.8V, I/O: 3.3V/internal: 1.5V, I/O: 2.5V/internal: 1.5V)
  • Low power consumption (Internal cell: 0.054 µW/MHz/gate, 1.8V, Typ.)
  • Drivability (IOL=2,4,8,12mA at 3.3V, IOL=1.5,3,6,9mA at 2.5V, IOL=1,2,4,6mA at 1.8V, IOL=0.75,1.5,3,4.5mA at 1.5V)
Macro Cells RAM, ROM, MCU, PLL, LVDS, RSDS, and various types of macro cells can be implemented
Packages 48-pin to 256-pin QFP, PBGA, PFBGA, QFN

Page Top

S1K60000Series

Status MP
Series S1K60000Series
Features
  • Ultra large scale integration (0.25 µm CMOS, using 3-, 4- or 5-layer interconnect process,
    number of raw gates: 3,900,000 Max.)
  • High-speed operation (Internal gate delay: 106ps/2.5V, 2-input NAND Typ.)
  • Selectable power supply voltage: Using single power supply: (2.0 V, 2.5 V)
    Using dual power supply: (I/O: 3.0 V, Internal: 2.5 V, I/O: 3.3 V, Internal: 2.0 V)
  • Low power consumption (Internal cell: 0.09 µW/MHz/gate, 2.5V, Typ.)
  • Drivability (IOL = 0.1, 1, 3, 6, 12, 24 mA at 3.3 V, IOL = 0.1, 1, 3, 6, 9, 18 mA at 2.5 V,
    IOL = 0.05, 0.3, 1, 2, 3, 6 mA at 2.0 V)
Macro Cells RAM, ROM, Flash, MCU, PLL, LVDS, RSDS, and various types of macro cells can be implemented
Packages 48-pin to 256-pin QFP, PBGA, PFBGA, QFN

Page Top

S1K50000Series

Status MP
Manual PDF S1K50000 Series Design Guide (1,984KB)
Series S1K50000Series
Features
  • Large scale integration (0.35 µm CMOS, using 3-, or 4-layer interconnect process, number of raw gates: 1,450,000 Max)
  • High-speed operation (Internal gate delay: 136ps/3.3V, 2-input power-NAND Typ.)
  • Selectable power supply voltage: Using single power supply: (2.0 V, 2.5 V, 3.3 V)
    Using dual power supply: (I/O: 5.0 V, Internal: 3.3 V, I/O: 3.3 V, Internal: 2.5 V, I/O: 3.3 V, Internal: 2.0 V)
  • Low power consumption (Internal cell: 0.22 µW/MHz/gate, 3.3V, Typ.)
  • Drivability (IOL = 0.1, 1, 3, 8, 12, 24 mA at 5.0 V, IOL = 0.1, 1, 2, 6, 12 mA at 3.3 V, IOL = 0.1, 0.5, 1, 3, 6 mA at 2.5 V, IOL = 0.05, 0.3, 0.6, 2, 4 mA at 2.0 V)
Macro Cells RAM, ROM, Flash, MCU, PLL, analog cells, LVDS, RSDS, and various types of macro cells can be implemented
Packages 48-pin to 256-pin QFP, PBGA, PFBGA, QFN, WCSP

Page Top