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Epson ASIC User Interface

The following flow chart shows the ASIC design data interface with Epson.

Library Pack Library Pack Library Pack Simulation result (APF) Timing Error List Vcd2apf

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Library Pack

Library Pack is a pack of libraries for logic synthesis and netlist simulations along with their manuals. Unlike a design kit, it is a pack of libraries only. Therefore, users can use it on EDA tools to suit their way of designing.

In the previous user interface design flow using the design kit, users need to generate and simulate APF files (in the Epson's original simulation pattern format). Meanwhile, in the new design flow with the library pack, users only need to send us VCD files of simulation results obtained with their test bench. This will greatly help users reduce design time.

However, Epson needs an information file (template) to convert VCD files into APF format. Generate the template using the Vcd2apf converter and send it to Epson together with VCD files.

Supported libraries

Library Pack supports the following ASIC series and EDA tools. If it is required, please contact an Epson sales representative in your region.

Supported ASIC series

Technology 0.6um 0.35um 0.25um 0.18um
Gate Array S1L30000 S1L35000 S1L50000
S1L60000 (S1L70000)
Embedded Array - (S1X35000) S1X50000 S1X60000 (S1X70000)
Standard cell - - S1K50000 S1K60000 S1K70000

Supported EDA tools

Category EDA tool name
Logic synthesizer Design Compiler
Simulator Verilog-XL, NC-Verilog, ModelSim (Verilog), ModelSim (VHDL)

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APF is an Epson original simulation pattern format. Basically it is a simple 0/1 table format. The outline is shown in the following table:

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Timing Error List

To analyze timing error messages in a log file output by the simulator is difficult, because errors are simply output in the order of occurrence. Therefore, Epson generates a timing error list in which error messages are sorted by instance and error type, and the error occurrence times are changed to offset time and cycle numbers. The list is sent to users in the format shown below.

The outline of timing error list is as follows:

(1) Instance line

Letter string following on "I=" The name of the instance in the cell where the timing error occurred
Letter string following on
the instance name
An error type is shown if the error is special one
Inside of "( )" Input pin name, the conditions, error type, and specification value.

(2) Data line

The 1st number The timing value of simulation result. Because the value is smaller than the one specified, the error occurred
The number followed by "/" Offset time in the cycle where the error occurred
The number following "/" Cycle number where the error occurred

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