Epson to Release Specialized Display Controller for Camera-Equipped GSM Mobile Phones

- TOKYO, Japan, November 26, 2003 -

Seiko Epson Corporation ("Epson") has developed the latest display controller chip in its series of Mobile Graphics Engines. The new controller, known as the S1D13716, has been optimized for camera-phones designed to work on the GSM network, the standard for mobile communications in Europe and much of the rest of the world. Samples, priced at 800 yen, are expected to begin shipping in the near future.

The S1D13716 has been designed specifically for the growing GSM camera-phone market in Europe and abroad. It has been optimized for driving active-matrix color liquid-crystal panels up to the QCIF class and supports VGA-class cameras, both of which are expected to be the mainstream in European markets. The controller comes with the GSM-standard 1.8V base-band CPU ("Base Band Engine") interface, the I2C bus camera needed for GSM phones, and LED control circuitry. By assuming the processing load for displaying images, the controller frees up the system CPU. It also helps decrease mobile phone power consumption. Set-makers will benefit from the low cost and ease with which they can realize display systems. By relieving the load on product developers, this controller will help set-makers shrink their development cycles.

The controllers in the Mobile Graphics Engine series occupy a key position among Epson's devices for mobile equipment, and Epson is committed to responding to customer needs by broadening and enhancing this line of products for tomorrow's multi-function camera-phones.

General specifications of the S1D13716

Embedded memory	112 KB
Camera interface	VGA (approx. 310,000 pixels) max.; I2C bus interface
YUV-RGB conversion	Built-in YUV-RGB converter circuits
Host interface	80x series / 68x series CPU Indirect 8-bit parallel interface
LCD interface	Two interfaces; 132 x 176 pixels max. Embedded RAM type
Display colors	Simultaneous display of 256 colors & 65,000 colors
JPEG codec	Built-in hardware JPEG codec Display image encode support
Display functions	Hardware rotation (SwivelViewTM); overlay display, etc.
LED control	For white backlight and for illumination (RGB)
Input clock	32.768 KHz external clock multiplied by built-in PLL
Operating voltage	3.0V for I/O and 1.65V to 3.6V for core
Package	112-pin PFBGA (8 x 8 x 1.2 mm; 0.65 mm pitch)